1. Field of the Invention
The present invention relates to a delta-sigma A/D converter using a delta-sigma modulator, and more particularly to a delta-sigma A/D converter using a second or higher order delta-sigma modulator, which is capable of generating a full-scale digital output while preventing occurrence of noise produced when the input signal level is equal or close to a full-scale level.
2. Prior Art
Conventionally, there is known a delta-sigma A/D converter which oversamples an analog input signal, subjects the oversampled analog input signal to a delta-sigma modulation (.DELTA..SIGMA. modulation) into a digital bit stream of 1 bit, and filters the bit stream into multi-bit digital data. The prior art A/D converter typically has a basic construction e.g. as shown in FIG. 1, wherein the A/D converter is comprised of a delta-sigma modulator (hereinafter referred to as ".DELTA..SIGMA. modulator") 1 and a decimation filter 2. The .DELTA..SIGMA. modulator 1 may be comprised of an integrator 11 which integrates the difference between an oversampled input signal Si and positive and negative feedback reference voltages .+-.VREF, and a 1-bit quantizer 12 which subjects the integrated value from the integrator 11 to 1-bit quantization to produce a 1-bit digital bit stream BS, and a feedback reference voltage selector 13 which selects the feedback reference voltage +VREF or -VREF in response to an output from the 1-bit quantizer 12 and feeds back it to the integrator 11. The decimation filter 2 extracts low-frequency components corresponding to the analog input signal Si, contained in the bit stream BS from the .DELTA..SIGMA. modulator 1 and converts the low-frequency components into multi-bit data to thereby output multi-bit digital data Do corresponding to the analog input signal Si.
Generally, in the case of a .DELTA..SIGMA. modulator which is a first-order type, the feedback reference voltage .+-.VREF is set to a value that is equal to the specified maximal level of the analog input signal such that full-scale digital data (0111 . . . 1 or 1000 . . . 1) are obtained when the analog input signal level is equal to the specified maximal level. In the case of a .DELTA..SIGMA. modulator which is a second or higher order type, however, the signal-to-noise ratio S/N sharply decreases when the analog input signal level assumes a value equal or close to the feedback reference voltage .+-.VREF, as shown in FIG. 2, as is known in the art.
To overcome this disadvantage, there has been proposed by U.S. Pat. No. 4,851,841 an A/D converter which is capable of obtaining full-scale digital data when the analog input signal level assumes a value at which the maximum analog-to-noise ratio S/N is obtained as shown in FIG. 2, by limiting the maximum analog input signal level of the .DELTA..SIGMA. modulator 1 to 80% of the feedback reference voltage .+-.VREF, for example, and setting the gain of the decimation filter 2 at a later stage of the .DELTA..SIGMA. modulator to 1.25 times that which is suitable for the decimation filter 2 of FIG. 1.
This proposed delta-sigma A/D converter wherein the maximum analog input signal level is limited to 1/G (=0.8) must have a filter characteristic such that the later-stage decimation filter has a gain of G (=1.25). To this end, all the filter coefficients of the decimation filter have to be set to G. The setting of the filter coefficients, is, however, very troublesome and costly, and therefore it is very difficult to change the gain of the decimation filter once it has been set.
Thus, in the prior art delta-sigma A/D converter, the gain of the .DELTA..SIGMA. modulator is directly determined by the gain of the decimation filter which is difficult to change, making it impossible to easily change the analog input signal level at which full-scale data is obtained.
Further, the former-stage .DELTA..SIGMA. modulator has to be designed so as to match the later-stage decimation filter, which reduces the degree of design freedom.